Prior programmable memories, as well as other integrated circuit devices, have utilized multi-gate structures. For example, a split-gate non-volatile memory (NVM) cell includes a select gate (SG) and a control gate (CG) that are used to add and remove charge from a charge storage layer. These select gates (SGs) and control gates (CGs) are typically formed in different processing steps during the fabrication process for NVM systems including split-gate NVM cells. Other multi-gate NVM cells have also been used for NVM systems. For example, triple-gate and other dual-gate NVM cell structures have been utilized for NVM systems. Further, multi-gate structures have been utilized in other integrated devices that are not NVM systems.
Reliability failure and/or undesirable performance variations can occur due to process variations and/or process tolerances for the semiconductor processing that is used to fabricate multi-gate structures. For example, program speed for different split-gate NVM cells within an NVM cell array can vary due to differences in the relative sizes and dimensions of select gates (SGs) and control gates (CGs) for split-gate NVM cells. These speed variations can cause performance problems with the operation of the NVM system including the split-gate NVM cell array. Similarly, differences between multi-gate structures within other integrated circuits, such as differences between other types of multi-gate NVM cells within NVM systems, can cause performance variations that lead to performance degradation.